The present invention relates to an analog to digital (A/D) converter, and in particular, it relates to a pipelined A/D converter that performs analog to digital conversion through the use of conversion blocks divided into a plurality of stages.
A typical A/D converter which performs analog to digital conversion through the use of several numbers of converting blocks is one that performs the two-step parallel method. With reference to FIG. 9, this method is performed by an A/D converter having a (a+b) bit analog to digital converter (ADC) unit composed of two blocks of an upper a-bit ADC and a lower b-bit ADC. More specifically, the A/D converter comprises sample-and-hold circuit (SHC) 1 which holds an analog signal at a constant value during its analog to digital conversion, upper ADC unit 2 which outputs an a-bit digital value, a-bit digital to analog (DAC) unit which converts the a-bit digital value into an analog value, adder 4 which obtains a difference between the analog signal held at SHC 1 and the analog signal derived from the DAC unit 3 and outputs a conversion residue representing a quantization error resulting from the conversion performed by the upper ADC unit 2, amplifier 5 which amplifies the conversion residue output from the adder 4, lower ADC unit 6 which outputs a b-bit digital value, latch circuit 7 which is coupled to ADC unit 2 and ADC unit 6 and outputs a digital signal which includes the a-bit digital value and the 6-bit digital value, and timing controller 8 which controls operation of the above described circuits.
The SHC 1 samples the analog input signal in synchronization with clock timing signals from the timing controller 8 and outputs sample values until lower ADC unit 6 completes its conversion. An output signal from SHC 1 is converted into an a-bit digital value by the upper ADC unit 2. This A/D converted output is again converted into an analog signal by a-bit DAC unit 3, then a difference between the analog signal output by DAC unit 3 and the output signal from the SHC 1 is obtained by adder 4. The difference determined by adder 4 is output as a conversion residue, which is then amplified in amplifier 5. The amplified output from the amplifier 5 is converted into a b-bit digital value by lower b-bit ADC unit 6. Then, the upper and the lower digital values are output as a (a+b) bit output by latch circuit 7. When such an analog to digital conversion operation is performed by dividing the conversion into several steps of sub-blocks, there always arises a problem that any mismatching between analog to digital converting blocks results in differential non-linearity errors. This is mainly caused by the offset voltages of respective analog to digital converting blocks, or dispersions in the gains in the blocks. These offset voltages or dispersions in gain cause a difference between the output voltage range of the amplifier 5 and the input voltage range of the lower ADC unit 6.
A two-step parallel A/D converter described in U.S. Pat. No. 4,875,048 provides a gain correcting circuit for the DAC unit 3 and a reference voltage generating circuit for the lower ADC unit 6. The reference voltage generating circuit adjusts reference voltages for the lower ADC unit 6 on the basis of the step voltage of the output of the DAC unit 3. However, differential non-linearity errors remain when the amplifier 5 have an offset voltage or a mismatched gain.
A co-pending U.S. patent application Ser. No. 907,524 filed on Jul. 2, 1992 describes a pipelined A/D converter provided with digital correction logic for correcting mismatches between a plurality of AD/DA sub-blocks. However, the digital correction logic cannot correct the differential non-linearity errors within a range of .+-.1 least significant bits (LSB). The conversion characteristics of the converter described in U.S. patent application Ser. No. 907,524 filed on Jul. 2, 1992 can be seen as shown in dotted lines in FIG. 10.
The references "A 10-bit 30 MHz Two-Step Parallel A/D Converter" Japanese Society of Electronics Information & Communications, 1990 Spring National Convention Proceedings, SA-3-1, pp. 1-403,404; and "A 10b 30 MHz Two-Step Parallel Bi-CMOS ADC with Internal S/H" IEEE ISSCC90 pp 162-163, Feb., 1990 describe an A/D converter which employs a technique called "overlapped interpolation method". Such an A/D converter is shown in FIG. 11. This A/D converter is based on the two-step parallel method with upper 6 bits and lower 5 bits. In the A/D converter shown in FIG. 11 in order to correct a matching error between the upper conversion and the lower conversion, the lowermost bit of the upper 6 bits and the uppermost bit of the lower 5 bits are overlapped, thereby providing a 10 bit output. The lower conversion is carried out after dividing the range of the reference voltage which has been specified by the upper conversion into 32 equal partitions, then amplified. Thus, operating errors in the lower comparator become the reciprocal of a gain, thereby substantially reducing errors occurring in the lower conversion. Further, because a reference voltage to be used in the lower conversion is generated on the basis of a reference voltage being used in the upper conversion, an A/D converter having a small differential non-linearity error is capable of being realized.
Although the above conventional technique is very convenient for obtaining a small differential non-linearity error without adjustment, it has the following disadvantages.
Whereas the lower conversion is performed following the upper conversion, the analog input signal must be held at a 10 bit precision during the whole period of time of such conversion. Thus, a fast, high precision SHC is required.
Further, differential amplifiers which produce a reference voltage for the lower conversion are needed in as many numbers as required corresponding to the upper resolution desired. Also, gains of the differential amplifiers must be strictly controlled.
Therefore, because of the above described disadvantages the circuit configuration of the A/D converter becomes complicated, and the circuit scale accordingly expands, resulting in an increased chip area and increased power consumption.